Tema: Como calcular los timings "raros" de las memorias?

Buenas! Todos conocesmos los timings típicos, es decir, cas, tras, trcd, trp, que son los típicos 2-2-2-5.

Lo que me tiene muy intrigado es el resto de valores que aparecen en mi placa (a8n-sli):

TRC:
TRFC:
TRWT:
TWR:
1T/2T

Me gustaría saber que valores darles, o si hay alguna fórmula para darles un valor aproximado.
Mi memoria es una OCZ Gold BH-5 a 3.0Vdimm

Muchas gracias.

eso digo yo,alguien lo sabe?

me parece que nos interesa a muchos de nosotros...

Bueno, pues escribí un mail al soporte de OCZ, y me respondieron lo siguiente:

Trfc = 19
Trc = 16
Trwt = 3 or 2 (2 is very tight...3 would be better)
Twr = 3 for stability...change to 2 if your system will stay stable.

Sin embargo, en un foro de overclocking estadounidense, un gurú decía que para las OCZ, estos timings son buenos:

Trfc = 14
Trc = 9
Trwt = 2
Twr = 2

Los estoy probando ahora mismo a 1T con el prime, mañana os digo si es estable a 3 voltios y 200 fsb.

podrias xplicar algo mas acerca de los timings y tal???

Explicar algo acerca de los timings?
Qué quieres saber en concreto?
Básicamente son los nanosegundos que tarda en direccionarse una posición de la memoria RAM, por tanto, cuanto más pequeños, más rápido irá nuestro sistema.
Por supuesto, hace falta memoria de calidad para poder poner unos timings bajos.

una CORSAIR???

Hay muchas memorias buenas, más que en la propia marca, hay que fijarse en los chips que montan.

En esta página puedes verlos tu mismo:
http://kattchan.blog.ocn.ne.jp/yashichi ... _229c.html

la 5400 UL dicen kes la poll...

Habeis visto las OCZ PC3200 o 3500 Dual Change tambien son excelentes memorias y que por cierto las latencias estan bajitas... :wink:
Salu2!!

CAS Latency Control(tCL)

Settings = Auto, 1, 1.5, 2, 2.5 3, 3.5, 4, 4.5.

This is the first timing that most ram companies rate their ram with. For example, you might see RAM rated at 3-4-4-8 @275mhz. this is the 3, in that situation. 2 yields the best performance, CAS 3 usually gives better stability. Please note; if you have Winbond-BH-5/6, you may not be able to use CAS3.

From Lost Circuits: http://www.lostcircuits.com/
“CAS is Column Address Strobe or Column Address Select. CAS controls the amount of time (in cycles (2, 2.5,& 3) between receiving a command and acting on that command. Since CAS primarily controls the location of HEX addresses, or memory columns, within the memory matrix, this is the most important timing to set as low as your system will stably accept it. There are both rows and columns inside a memory matrix. When the request is first electronically set on the memory pins, the first triggered response is tRAS (Active to Precharge Delay). Data requested electronically is precharge, and the memory actually going to initiate RAS is activation. Once tRAS is active, RAS, or Row Address Strobe begins to find one half of the address for the required data. Once the row is located, tRCD is initiated, cycles out, and then the exact HEX location of the data required is accessed via CAS. The time between CAS start and CAS end is the CAS latency. Since CAS is the last stage in actually finding the proper data, it's the most important step of memory timing.”

From Adrian Wong’s site: http://www.rojakpot.com/
“This BIOS feature controls the delay (in clock cycles) between the assertion of the CAS signal and the availability of the data from the target memory cell. It also determines the number of clock cycles required for the completion of the first part of a burst transfer. In other words, the lower the CAS latency, the faster memory reads or writes can occur. Please note that some memory modules may not be able to handle the lower latency and may lose data. Therefore, while it is recommended that you reduce the SDRAM CAS Latency Time to 2 or 2.5 clock cycles for better memory performance, you should increase it if your system becomes unstable. Interestingly, increasing the CAS latency time will often allow the memory module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM modules, try increasing the CAS latency time.”

Slight Influence on Bandwidth / Large Influence on Stability.

Suggested Settings for DFI: 1.5, 2, 2.5, and 3. (Lower = Faster)


RAS# to CAS# Delay(tRCD)

Settings = Auto, 0, 1, 2, 3, 4, 5, 6, 7.

This is the second timing that most ram companies rate there ram with. For example, you might see ram rated at 3-4-4-8@275mhz. This is the first 4, in that situation.

From Adrian Wong’s site: http://www.rojakpot.com/
”This BIOS feature allows you to set the delay between the RAS and CAS signals. The appropriate delay for your memory module is reflected in its rated timings. In JEDEC specifications, it is the second number in the three or four number sequence. Because this delay occurs whenever the row is refreshed or a new row is activated, reducing the delay improves performance. Therefore, it is recommended that you reduce the delay to 3 or 2 for better memory performance. Please note that if you use a value that is too low for your memory module, this can cause the system to be unstable. If your system becomes unstable after you reduce the RAS-to-CAS delay, you should increase the delay or reset it to the rated delay. Interestingly, increasing the RAS-to-CAS delay may allow the memory module to run at a higher clock speed. So, if you hit a snag while overclocking your SDRAM modules, you can try increasing the RAS-to-CAS delay.”

Large Influence on Bandwidth/ Stability.

Suggested Settings for DFI: 2-5 ----2 yields the best performance, and 4-5 yields the best over clock (5 is usually overkill). Usually cheaper RAM will not be able to use 2, and reach their max OC. (Lower = Faster)


Min RAS# Active Timing(tRAS)

Settings = Auto, 00, 01, 02, 03, 04, 05, 06, 07, 08, 09, 10, 11, 12, 13, 14, 15.

This is the fourth timing that most ram companies rate there ram with. For example, you might see ram rated at 3-4-4-8 @275mhz. this is the 8, in that situation.

From Adrian Wong’s site: http://www.rojakpot.com/
”This BIOS feature controls the memory bank's minimum row active time (tRAS). This constitutes the time when a row is activated until the time the same row can be deactivated. If the tRAS period is too long, it can reduce performance by unnecessarily delaying the deactivation of active rows. Reducing the tRAS period allows the active row to be deactivated earlier. However, if the tRAS period is too short, there may not be enough time to complete a burst transfer. This reduces performance and data may be lost or corrupted. For optimal performance, use the lowest value you can. Usually, this should be CAS latency + tRCD + 2 clock cycles. For example, if you set the CAS latency to 2 clock cycles and the tRCD to 3 clock cycles, the optimum tRAS value would be 7 clock cycles. But if you start getting memory errors or system crashes, increase the tRAS value one clock cycle at a time until your system becomes stable.”

It appears throughout the web that this is a much debated timing. Some may argue that 00, 05, or 10 is the faster/most stable. There probably isn’t a right answer for this one, it all depends on your ram. If you need a good starting point, usually most/all ram can achieve their max OC on 10 tRAS, even if one of the other settings is faster.

Slight Influence on Bandwidth/Stability.

Suggested Settings for DFI: Suggest you use only 00, and 5-10. I’d start with 8 and play around from there. (Lower = Faster)


Row Precharge Timing(tRP)

Settings = Auto, 0, 1, 2, 3, 4, 5, 6, 7

This is the third timing that most ram companies rate there ram with. For example, you might see ram rated at 3-4-4-8 @275mhz. this is the second 4, in that situation.

From Adrian Wong’s site: http://www.rojakpot.com/
”This BIOS feature specifies the minimum amount of time between successive ACTIVATE commands to the same DDR device. The shorter the delay, the faster the next bank can be activated for read or write operations. However, because row activation requires a lot of current, using a short delay may cause excessive current surges. For desktop PCs, a delay of 2 cycles is recommended as current surges aren't really important. The performance benefit of using the shorter 2 cycles delay is of far greater interest. The shorter delay means every back-to-back bank activation will take one clock cycle less to perform. This improves the DDR device's read and write performance. Switch to 3 cycles only when there are stability problems with the 2 cycles setting.”

Large Influence on Bandwidth/Stability.

Suggested Settings for DFI: 2-4 ----2 yields the best performance, and 4-5 yields the best stability when overclocking (5 is usually overkill). A lot of RAM will not be able to use 2, and reach their max OC. (Lower = Faster)


Row Cycle Time(tRC)

Settings = Auto, 7-22 in 1.0 increments.

From Adrian Wong’s site: http://www.rojakpot.com/
”This BIOS feature controls the memory module's Row Cycle Time or tRC. The row cycle time determines the minimum number of clock cycles a memory row takes to complete a full cycle, from row activation up to the precharging of the active row. Formula-wise, the row cycle time (tRC) = minimum row active time (tRAS) + row precharge time (tRP). Therefore, it is important to find out what the tRAS and tRP parameters are before setting the row cycle time. If the row cycle time is too long, it can reduce performance by unnecessarily delaying the activation of a new row after a completed cycle. Reducing the row cycle time allows a new cycle to begin earlier. However, if the row cycle time is too short, a new cycle may be initiated before the active row is sufficiently precharged. When this happens, there may be data loss or corruption. For optimal performance, use the lowest value you can, according to the tRC = tRAS + tRP formula. For example, if your memory module's tRAS is 7 clock cycles and its tRP is 4 clock cycles, then the row cycle time or tRC should be 11 clock cycles. However, if the row cycle time is too short, a new cycle may be initiated before the active row is sufficiently precharged. When this happens, there may be data loss or corruption.”

Large Influence on Bandwidth/Stability.

Suggested Settings for DFI: 7 yields the best performance, 15-17 yields the best stability/over clock. 22 is way overkill. Start at 16, and work your way down from there. 7 is usually much too tight for most average ram. Remember the tRC = tRAS + tRP formula. (Lower = Faster)


Row Refresh Cycle Time(tRFC)

Settings = Auto, 9-24 in 1.0 increments.

From the DFI BIOS: “This bios setting represents time to refresh a single row on the same bank of memory. This value is also the time interval between a refresh (REF command) to another REF command to different rows of the same bank. The tRFC value is higher than tRC as column access gates are not turned on during it’s issue.”

Large Influence on Bandwidth/Stability.

Suggested Settings for DFI: 9 is usually unreachable and 10 yields the best performance. 17-19 yields the best stability/over clock with 19 probably overkill. Start at 17 and work your way down. Most stable timing is usually set to 2-4 clocks higher than tRC. (Lower = Faster)


Row to Row Delay(also called RAS to RAS delay)(tRRD)

Settings = Auto, 0-7 in 1.0 increments.

From Adrian Wong’s site: http://www.rojakpot.com/
“This BIOS feature specifies the minimum amount of time between successive ACTIVATE commands to the same DDR device. The shorter the delay, the faster the next bank can be activated for read or write operations. However, because row activation requires a lot of current, using a short delay may cause excessive current surges. For desktop PCs, a delay of 2 cycles is recommended as current surges aren't really important. The performance benefit of using the shorter 2 cycles delay is of far greater interest. The shorter delay means every back-to-back bank activation will take one clock cycle less to perform. This improves the DDR device's read and write performance. Switch to 3 cycles or higher only when there are stability problems with the 2 cycles setting.”

Slight Influence on Bandwidth/Stability.

Suggested Settings for DFI: 00 yields the best performance and 4 yields the best stability/over clock (anything above 4 is probably overkill). 2 is probably your best bet. 00 sounds odd, but it has worked well for others, even at 260 MHz. (Lower = Faster)


Write Recovery Time(tWR)

Settings = Auto, 2, 3.

From Adrian Wong’s site: http://www.rojakpot.com/
“This BIOS feature controls the Write Recovery Time (tWR) of the memory modules. It specifies the amount of delay (in clock cycles) that must elapse after the completion of a valid write operation, before an active bank can be precharged. This delay is required to guarantee that data in the write buffers can be written to the memory cells before precharge occurs. The shorter the delay, the earlier the bank can be precharged for another read/write operation. This improves performance but runs the risk of corrupting data written to the memory cells. It is recommended that you select 2 Cycles if you are using DDR200 or DDR266 memory modules and 3 Cycles if you are using DDR333 or DDR 400 memory modules. You can try using a shorter delay for better memory performance but if you face stability issues, revert to the specified delay to correct the problem.”

Slight Influence on Bandwidth/Stability.

Suggested Settings for DFI: 2 yields better performance, and 3 yields better stability/over clock. (Lower = Faster)


Write to Read Delay(tWTR)

Settings: Auto, 1, 2

From Adrian Wong’s site: http://www.rojakpot.com/
”This BIOS feature controls the Write Data In to Read Command Delay (tWTR) memory timing. This constitutes the minimum number of clock cycles that must occur between the last valid write operation and the next read command to the same internal bank of the DDR device. The 1 Cycle option naturally offers faster switching from writes to reads and consequently better read performance. The 2 Cycles option reduces read performance but it will improve stability, especially at higher clock speeds. It may also allow the memory chips to run at a higher speed. In other words, increasing this delay may allow you to overclock the memory module higher than is normally possible. It is recommended that you select the 1 Cycle option for better memory read performance if you are using DDR266 or DDR333 memory modules. You can also try using the 1 Cycle option with DDR400 memory modules. But if you face stability issues, revert to the default setting of 2 Cycles.”

From the DFI BIOS: “This Bios setting specifies the write to read delay. Samsung calls this TCDLR (last data in to read command). It is measured from the rising edge and following the last non-mask data strobe to the rising edge of the next read command. JDEC usually specifies this as one clock.”

Slight Influence on Bandwidth/Stability.

Suggested Settings for DFI: 1 yields better performance, and 2 yields better stability/over clock. (Lower = Faster)


Read to Write Delay(tRTW)

Settings = Auto, 1-8 in 1.0 increments.

Paraphrased From Adrian Wong’s site: http://www.rojakpot.com/
”When the memory controller receives a write command immediately after a read command, an additional period of delay is normally introduced before the write command is actually initiated. As its name suggests, this BIOS feature allows you to skip (or raise) that delay. This improves the write performance of the memory subsystem. Therefore, it is recommended that you enable this feature for faster read-to-write turn-arounds. However, not all memory modules can work with the tighter read-to-write turn-around. If your memory modules cannot handle the faster turn-around, the data that was written to the memory module may be lost or become corrupted. So, when you face stability issues, disable (or raise the value) of this feature to correct the problem.”

From the DFI BIOS: “This field specifies the read to write delay. This is not a DRAM specified timing parameter, but must be considered due to the routing latencies on the clock forwarded bus. It is counted from the first address bus slot which was not associated with part of the read burst.”

Slight Influence on Bandwidth/Stability.

Suggested Settings for DFI: 1 yields better performance, and 4 yields better stability/over clock (4 is overkill). Recommend try 1 and move to 2 if unstable. (Lower = Faster)


Refresh Period(tREF)

Settings = Auto, 0032-4708 in variable increments.

1552= 100mhz(?.?us)
2064= 133mhz(?.?us)
2592= 166mhz(?.?us)
3120= 200mhz(?.?us)(seems to be a/ Bh-5,6 sweet spot at 250+mhz)
---------------------
3632= 100mhz(?.?us)
4128= 133mhz(?.?us)
4672= 166mhz(?.?us)
0064= 200mhz(?.?us)
---------------------
0776= 100mhz(?.?us)
1032= 133mhz(?.?us)
1296= 166mhz(?.?us)
1560= 200mhz(?.?us)
---------------------
1816= 100mhz(?.?us)
2064= 133mhz(?.?us)
2336= 166mhz(?.?us)
0032= 200mhz(?.?us)
---------------------
0388= 100mhz(15.6us)
0516= 133mhz(15.6us)
0648= 166mhz(15.6us)
0780= 200mhz(15.6us)
---------------------
0908= 100mhz(7.8us)
1032= 133mhz(7.8us)
1168= 166mhz(7.8us)
0016= 200mhz(7.8us)
---------------------
1536= 100mhz(3.9us)
2048= 133mhz(3.9us)
2560= 166mhz(3.9us)
3072= 200mhz(3.9us)
---------------------
3684= 100mhz(1.95us)
4196= 133mhz(1.95us)
4708= 166mhz(1.95us)
0128= 200mhz(1.95us)

Paraphrased From Adrian Wong’s site: http://www.rojakpot.com/
”This BIOS feature allows you to set the refresh interval of the memory chips. There are (several) different settings as well as an Auto option. If the Auto option is selected, the BIOS will query the memory modules' SPD chips and use the lowest setting found for maximum compatibility. For better performance, you should consider increasing the Refresh Interval from the default values (15.6 µsec for 128Mbit or smaller memory chips and 7.8 µsec for 256Mbit or larger memory chips) up to 128 µsec. Please note that if you increase the Refresh Interval too much, the memory cells may lose their contents. Therefore, you should start with small increases in the Refresh Interval and test your system after each hike before increasing it further. If you face stability problems upon increasing the refresh interval, reduce the refresh interval step by step until the system is stable.

From Sierra at ABXzone: The information below is taken from an old RAM guide. In a nutshell a memory module is made up of electrical cells. The refresh process recharges these cells, which are arranged on the chips in rows. The refresh cycle refers to the number of rows that must be refreshed.

"Periodically the charge stored in each bit must be refreshed or the charge will decay and the value of the bit of data will be lost. DRAM (Dynamic Random Access Memory) is really just a bunch of capacitors that can store energy in an array of bits. The array of bits can be accessed randomly. However, the capacitors can only store this energy for a short time before it discharges it. Therefore DRAM must be refreshed (re-energizing of the capacitors) every 15.6µs (a microsecond equals 10-6 seconds) per row. Each time the capacitors are refreshed the memory is re-written. For this reason DRAM is also called volatile memory. Using the RAS-ONLY refresh (ROR) method, the refresh is done is a systematic manner, each column is refreshed row by row in sequence. In a typical EDO module each row takes 15.6µs to refresh. Therefore in a 2K module the refresh time per column would be 15.6µs x 2048 rows = 32ms (1 millisecond equals 10-6 seconds). This value is called the tREF. It refers to the refresh interval of the entire array."

Here is an interesting discussion of tREF on the DFI forum: http://www.dfi-street.com/forum/showthread.php?t=10411

Slight Influence on Stability/Bandwidth.

Suggested Settings for DFI: It appears that tREF, like the tRAS, is not an exact science. It also seems that the 15.6us, and 3.9us settings work well, and that the 1.95us settings give lower bandwidth. The unknown (?.?us) are shots in the dark. A lot of users are finding setting 3120= 200mhz(?.?us) gives the best balance of performance, and stability, but this will probably vary greatly from one type of RAM to another.


Write CAS# Latency(tWCL)

Settings = Auto, 1-8

Paraphrased from Lost Circuits: http://www.lostcircuits.com/
”Variable Write CAS Latency (tWCL): Conventional SDRAM including DDR I uses random accesses as the name implies. This means that the controller is free to write to any location within the physical memory space, which, in most cases, means that it will write to whichever page is open and to the column address closest to the (CAS) strobe. The result is a write latency of 1T, as opposed to read or CAS-Latency values of 2, 2.5 or 3. (This setting should almost) always be set to 1 unless using DDRII.”

Large Influence on Stability/ Unknown Influence on bandwidth.

Suggested Settings for DFI: Most people can only post using Auto or 1. RGone over at DFI-Street says that #5 in this setting works on his board with “any” brand or size and speed of memory! Recommend try 1.

Traductor gugel va de perlas

Salu2

jajaja,ya lo mire en los apuntes

Iniciado por Murphi

Traductor gugel va de perlas

Umm lo que traduce google al ser lenguaje técnico es una auténtica xxxxx, a ver si saco tiempo de algún sitio y me pongo a traducirlo, o a ver si alguien más se anima, y lo ponemos por aquí como posit.

Por cierto que os recomiendo de la página de Adrian Wong’s su guia de optimización de la BIOS no tiene desperdicio.

busca esos datos en español y acabas antes

Esta guia sobre latencias esta vastante bien y en español:
http://www.hardcore-modding.com/modules ... pic&t=8648

sl2

si ya sabia yo ke eso de traducir no era muy practico x_D

Iniciado por Byelink

Por cierto que os recomiendo de la página de Adrian Wong’s su guia de optimización de la BIOS no tiene desperdicio.

Y el link............



Salu2

so digo yo,no estara en chino no?? ---> Adrian Wong

tios, que está arriba: http://www.rojakpot.com/

coño,pos dilo x_DD

coño, pos dicho XD

Pero.........Guia de BIOS Pagando Jajajajajajaja

Que le den por donde amargan los pepinos al mendas este

salu2

Iniciado por Murphi

Pero.........Guia de BIOS Pagando Jajajajajajaja

Que le den por donde amargan los pepinos al mendas este

salu2

jojo,ya te digo